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EDITING: sa1100.S

/* SPDX-License-Identifier: GPL-2.0-only */
/* arch/arm/include/debug/sa1100.S
 *
 * Debugging macro include header
 *
 *  Copyright (C) 1994-1999 Russell King
 *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*/

#define UTCR3		0x0c
#define UTDR		0x14
#define UTSR1		0x20
#define UTCR3_TXE	0x00000002	/* Transmit Enable                 */
#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)         */
#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */

.macro	addruart, rp, rv, tmp
		mrc	p15, 0, \rp, c1, c0
		tst	\rp, #1			@ MMU enabled?
		moveq	\rp, #0x80000000	@ physical base address
		movne	\rp, #0xf8000000	@ virtual address

@ We probe for the active serial port here, coherently with
		@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
		@ We assume r1 can be clobbered.

@ see if Ser3 is active
		add	\rp, \rp, #0x00050000
		ldr	\rv, [\rp, #UTCR3]
		tst	\rv, #UTCR3_TXE

@ if Ser3 is inactive, then try Ser1
		addeq	\rp, \rp, #(0x00010000 - 0x00050000)
		ldreq	\rv, [\rp, #UTCR3]
		tsteq	\rv, #UTCR3_TXE

@ if Ser1 is inactive, then try Ser2
		addeq	\rp, \rp, #(0x00030000 - 0x00010000)
		ldreq	\rv, [\rp, #UTCR3]
		tsteq	\rv, #UTCR3_TXE

@ clear top bits, and generate both phys and virt addresses
		lsl	\rp, \rp, #8
		lsr	\rp, \rp, #8
		orr	\rv, \rp, #0xf8000000	@ virtual
		orr	\rp, \rp, #0x80000000	@ physical

.endm

.macro	senduart,rd,rx
		str	\rd, [\rx, #UTDR]
		.endm

.macro	waituartcts,rd,rx
		.endm

.macro	waituarttxrdy,rd,rx
1001:		ldr	\rd, [\rx, #UTSR1]
		tst	\rd, #UTSR1_TNF
		beq	1001b
		.endm

.macro	busyuart,rd,rx
1001:		ldr	\rd, [\rx, #UTSR1]
		tst	\rd, #UTSR1_TBY
		bne	1001b
		.endm

CANCEL

Name	Type	Size	Modified	Actions
↩ ..	DIR	—	—
📄 8250.S	S	1 KB	2025-09-28 21:39	EDIT
📄 asm9260.S	S	645 B	2025-09-28 21:39	EDIT
📄 at91.S	S	1 KB	2025-09-28 21:39	EDIT
📄 bcm63xx.S	S	643 B	2025-09-28 21:39	EDIT
📄 brcmstb.S	S	5.5 KB	2025-09-28 21:39	EDIT
📄 clps711x.S	S	767 B	2025-09-28 21:39	EDIT
📄 dc21285.S	S	842 B	2025-09-28 21:39	EDIT
📄 digicolor.S	S	648 B	2025-09-28 21:39	EDIT
📄 exynos.S	S	1.1 KB	2025-09-28 21:39	EDIT
📄 icedcc.S	S	1.4 KB	2025-09-28 21:39	EDIT
📄 imx-uart.h	H	5.3 KB	2025-09-28 21:39	EDIT
📄 imx.S	S	1.2 KB	2025-09-28 21:39	EDIT
📄 meson.S	S	771 B	2025-09-28 21:39	EDIT
📄 msm.S	S	1 KB	2025-09-28 21:39	EDIT
📄 omap2plus.S	S	2 KB	2025-09-28 21:39	EDIT
📄 palmchip.S	S	199 B	2025-09-28 21:39	EDIT
📄 pl01x.S	S	769 B	2025-09-28 21:39	EDIT
📄 renesas-scif.S	S	1 KB	2025-09-28 21:39	EDIT
📄 s3c24xx.S	S	775 B	2025-09-28 21:39	EDIT
📄 s5pv210.S	S	891 B	2025-09-28 21:39	EDIT
📄 sa1100.S	S	1.6 KB	2025-09-28 21:39	EDIT
📄 samsung.S	S	1.9 KB	2025-09-28 21:39	EDIT
📄 sti.S	S	1022 B	2025-09-28 21:39	EDIT
📄 stm32.S	S	1.1 KB	2025-09-28 21:39	EDIT
📄 tegra.S	S	6.3 KB	2025-09-28 21:39	EDIT
📄 uncompress.h	H	222 B	2025-09-28 21:39	EDIT
📄 ux500.S	S	1 KB	2025-09-28 21:39	EDIT
📄 vexpress.S	S	1.2 KB	2025-09-28 21:39	EDIT
📄 vf.S	S	923 B	2025-09-28 21:39	EDIT
📄 vt8500.S	S	774 B	2025-09-28 21:39	EDIT
📄 zynq.S	S	1.2 KB	2025-09-28 21:39	EDIT